EDA

9 Benefits of Semiconductors EDA

Analog / Digital on Rails

Disruptive Electronic Design Automation

ANALOG ON RAILS BASIC

SYNCHRONIZED, CORRECT BY CONSTRUCTION™

Complete OA Analog IC platform.
Better than VXL. Far less cost.

EDA - Analog Rails Basic

DIGITAL ON RAILS

INCLUDES HUGE BUILT-IN LOGIC LIBRARY

Complete Mixed-signal IC platform. Integrated with Analog On Rails Basic.

ANALOG ON RAILS PREMIUM

REDUCE DESIGN TIME BY 10x WITH AUTOMATION

Basic + Digital + Automatic Analog.
A disruptive IC design platform.

Built on the industry standard Open Access (OA) from scratch without legacy code. Analog On Rails Basic uses the same database as VXL. Never have a DRC or LVS violation. Cross probing and backannotation always. Infinite supply of multithreaded co-simulation licenses.

Includes synthesis with static timing optimization, automatic cell characterization, and fully integrated into the Analog On Rails platform, all with cross probing, capacitance backannotation, 3D views, etc. Automatic feedback loops. No manual intervention is needed.

Reduce the former “full custom” IC design cycle from months down to hours. The Analog On Rails mixed-signal platform is built around the automation tools. With the ability to go bottom to top to bottom to top quickly, do not fear last-minute changes… embrace them.

  • OA native database. Plays with Virtuoso
  • Built-in abutable backannotating PCells
  • Graphical PCell generator
  • Built-in stdcells with behavioral views
  • Over 100 behavioral symbols
  • Infinite AMS and HB simulator licenses
  • Multithreaded transistor simulator
  • Co-simulates with digital behavior
  • Synchronized schematic, layout, wave
  • DRC/LVS Correct By Construction™
  • Cross probes always
  • Highly accurate parasitic extraction
  • Built-in analog and RF measurements
  • Backannotate waveform’s transient point
  • Corners built in 
  • Pushbutton RTL to Gate level synthesis
  • Creates schematic with backannotation
  • Place and route over 1M cells
  • Automatic feedback loops. Let it bake
  • Built-in logic cells synthesizable
  • Automatic timing characterization
  • Static Timing Optimization built-in
  • Digital behavioral views of all cells
  • Analog behavioral views of all cells
  • Infinite System Verilog licenses
  • Built-in power mesh and clock trees
  • Auto pin based on parent’s flight lines
  • Co-simulates with Analog
  • Integrated into analog system

*Includes all functionality of Basic Rails 

  • Automatic migration tool
  • Optimizer runs DC, AC, tran over corners
  • Automatic differential structures
  • Automatic electrically aware router
  • Differential route with shields
  • Differential aware density filler
  • Automatic power supply mesh
  • Automatic compactor
  • Delete autoroutes, update, re-autoroute
  • EM diagnostics. See EM% on the layout
  • Click on 2 points. Get IR drop
  • Cx and RCx wiring extraction
  • Includes Basic and Digital Rails
  • Sensitivity pinpoints measurement’s culprit
  • Monte Carlo runs on infinite licenses

Co-simulation along with an infinite number of Xyce/Spice licenses

Also included is Harmonic Balance and built-in RF measurements, such as transient noise. Users can also optionally simulate with 3rd party Hspice compatible simulators.

Synthesis with a press of a button

Users can automatically generate the gate-level netlist and schematic based on their RTL code with a simple graphical interface in the same design environment as Analog On Rails. It’s so easy, an analog circuit designer can do it.

Optimization made easy

Place your measurements and analysis components in our OA-based schematic, choose properties (including transistor operating regions) to optimize, and go to lunch. Return to see the final circuit sized according to spec over all corners. Runs AC, DC, and transients at the same time on multiple machines. 

Manual DRC/LVS Correct By Construction™ layout

Much more powerful than DRC and LVS, the users cannot make a DRC or LVS  violation. Primitives (fets, caps, resistors, bipolars, and differential structures) are generated automatically based on the technology file. No CAD scripts are required. Structures snap/repel/permute based on schematic connectivity. Collision avoidance on wiring. Once again, it is impossible for users to make violations. 

Digital Place and Route

Digital Rails makes digital place and route trivial due to built-in logic cells, synthesis, timing characterization, RCx, static timing tools, clock trees, and automatic flight line-based pin generators. The Digital Rails place and route tool automatically runs timing feedback loops and adjusts the layout, allowing users to click onto the PNR button and not require any manual intervention in order to come up with the fastest clock frequencies possible for the given RTL code being processed. The parasitics will always be backannotated into the schematic. The resulting block will instantiate perfectly onto the analog grid system for use at the higher level of the design.

Automatic Analog Routing

Our best feature. Low capacitive routes. Our multi-block and  Transistor-level router also handles differential signals, with wire extensions and shields. We route 100% of the signals and ensure they are DRC correct. Routes are EM-friendly. Also includes a power supply mesh.  Well taps are automatically generated. Preroutes optional. 

Measurements and analysis components in the schematic

Place settling time, overshoot, bandwidth, phase margin, risetime, and etc. components into the schematic, along with multiple analysis components (AC, DC, tran, pss, etc). Corner setups are included in the analysis components. 

Huge built-in logic library

A vast set of process-independent parameterized (w_pmos, w_nmos, L)  digital library topologies ships with Analog On Rails. Standard cell layouts will be automatically generated. We don’t need your digital  layouts. Works in both the analog editor and digital P&R. The  substrate (sub) terminal is isolated from the vssd terminal, where the  users can optionally tie the substrate to the digital ground or isolate the supply from touching the main substrate. All logic cells contain behavioral views. Rise/fall times based on Cload, W, L, Cx.

Automatic analog placement and differential structures

Set auto-match on, press the “P” button, and enjoy the show. We know analog, and you can expect to see common centroid structures with guard rings, multiple dummies, and extended wells to reduce the STI stress and well proximity effects. Don’t trust our layouts? Our product begins with “analog”.

Sensitivity Analysis

All measurements receive the variation and the largest culprits, both the devices and their parameters, causing the variation. 

Automatic Cell Characterization

Characterization is automatically done in Digital Rails. Upon PDK  creation, merely define the corners, the slope steps, and the capacitor loads. The liberty formats will be automatically generated and will be  used by our built-in static timing tool. 

Advanced Layout Diagnostics

Cx backannotated into the schematic, RCx, selected net RCx, EM, IR drop, resistance between 2 points in the layout… we do it all! 

NEVER LOSE Cross-Probing

Even when flattening the layout, Analog On Rails continues to cross-probe the schematic and layout. The circuit designer can always follow the signal… even in 3D! 

SYSTEM VERILOG Included

An infinite number of System Verilog simulator licenses are included in  Digital Rails. The built-in logic cells contain Verilog views that allow  users to run system simulations easily. Just add the top-level stimulus. 

DIFFERENTIAL AWARE Density Fill

Because of our focus on differential signals, we provide density fill that is aware of your sensitive routes and differential structures/wires. 

Simulate Layout Parasitics AT ALL TIMES

Why wait months to get layout parasitics, such as STI Stress Effects, length of diffusion, and well proximity? DC Currents can be off by 20% without knowing these layout-generated values. Now setting reltol has more meaning. 

BEHAVIORAL VIEWS Included

All logic cells contain both analog and digital behavioral views. The output slopes are a function of the supply,  widths, lengths, and capacitive loads. This is especially important after post layout (RCx) extraction. The full chip simulation can be run with the included digital and mixed-signal simulators. 

Process MIGRATION TOOL

Easily retarget your schematics from one process to another. Move designs from 180n to 12n easily. Migrate => Optimize <=>  Sensitivity <=> Automatically layout. Bada bing, bada boom… it’s done! 

Why Analog/Digital On Rails?

Analog/Digital On Rails is a complete expert system that is intended to reduce the time to market on your mixed-signal chips by a huge factor. There is a methodology and flow built into it. The usage is a paradigm shift and is several generations beyond what is out in the market.

REDUCE CYCLE TIMES

  1. Because of layout automation, real parasitics are used during the design phase.
  2. Last-minute changes? No problem. Blow away the autoroutes, edit, and then autoroute again.
  3. Place your DUT into your already established test benches (we can supply them), change the spec, and run the optimizer. Saves weeks of trading off between specs and operating regions (set minimum vds-vdsat).
  4. Correct By Construction™. No more DRC or LVS errors.
  5. Our manual editor is much more powerful than our competitors. Dummies made easy, automatic via insertion, auto abut, repel, etc.

SAVE AREA

  1. No need to be conservative on layouts. Legacy blocks are designed with 20%  area thrown away to leave room for design changes. No longer needed.
  2. The circuit designer can utilize black space during the design and make sizes bigger for matching or increasing headroom. The designer can also trade sizes (rout vs. gm) for layout efficiency.
  3. Sensitivity analysis based on the REAL layout parasitics can allow the circuit designer to be less conservative on sizes.
  4. No more top-down. Instead, quickly iterate between the bottom and top levels.
  5. Flattening hierarchies preserves connectivity. Feel free to smush it together!

IMPROVE QUALITY

  1. Your layout designer has no chance against our automatic router.  Our router is electrically aware. We know which nets are high impedance,  low impedance,  static, dynamic, etc. The router gets information from the simulation and runs automatically. Our router will keep capacitances low when needed, shield differential or sensitive nets, etc.
  2. The circuit designer controls the location of the devices at the rate of 30 seconds per device or can save time by running “mimic layout”, which places devices down in a similar manner to the user-selected design.
  3. Automatic built-in inter-digitized or side-by-side differential structures with perfectly symmetrical routing.
  4. Sensitivity analysis provides bulletproof designs.
  5. Reduced cycle time results in more verification time. No more last-minute scrambling and taking shortcuts.
  6. Optimize devices to meet specifications based on sensitivity to Vds, Vgs,  LOD, WPE, etc.

DIAGNOSTIC IMPROVEMENTS

  1. Backannotates ad, as, pd, ps, sb, sc, sd, sca, scb, scc, parasitic capacitance.
  2. Backannotates gate protection and hot well diodes.
  3. Voltages/currents backannotation tracks the waveform.
  4. Colorization of fets based on operating points and other alarms.
  5. EM. Set EM% on the pulldown. All segments and vias that exceed that value  are shown in the layout.
  6. IR drop. Click onto 2 points on a route. See the resistance and voltage drop through the segments and vias.
  7. Cross-probing between schematic, layout, and hierarchical editor at all  times.
  8. Sensitivity and mismatch analysis built-in.
  9. 3D view. Great feature when using with IR drop.

COMPATIBILITY

Open Access is our database. Plug and play with Virtuoso.

REDUCE CAD EFFORT

  1. Graphical PCells, or use our design rule-driven built-in PCells.
  2. Tools all work together. Analog On Rails is a complete design package. No customization is required.
  3. The “It’s So Easy, An Analog Circuit Designer Can Do It” PDK GUI puts the design group in complete control.
  4. Built-in Design and Data management will work with any backend version control system, but the user gets to see changes elegantly within the tool. Because we work within our source code, our system is better. We didn’t throw DM over the wall to 3rd party vendors. We took responsibility (think of Windows relying on 3rd party vendors to handle anti-virus, as opposed to the built-in security of Unix/Linux)
EDA Design Rule Check

COMPARISON TO INDUSTRY STANDARD ANALOG DESIGN PLATFORM:

Your Platform

  • Your platform is built on a fully customized platform.
  • Your platform is a bicycle attempting to kludge in a motor.
  • Your platform is made up of independent components.
  • Your platform tools are not synchronized.
  • Your platform layouts must run DRC and LVS.
  • Your platform layout designers can create unidentified routes.
  • Your platform has a decoupled simulation environment.
  • Your platform users analyze EM and parasitic effects post-layout.
  • Your platform is post-simulation-centric. Has a calculator.

Analog/Digital On Rails

  • Analog/Digital On Rails is based on built-in methodologies.
  • Analog/Digital OnRails is a motorcycle with pedaling capability.
  • Analog/Digital On Rails integrates..  “The whole is greater than the sum of its parts.” 
  • Analog/Digital On Rails is 100% synchronized.
  • Analog/Digital On Rails is DRC, LVS Correct By Construction™ AT ALL TIMES.
  • Analog/Digital On Rails does not allow unidentified routes.
  • Analog/Digital On Rails has simulation components in the schematic.
  • Analog/Digital On Rails passes simulation information to the router in advance.
  • Analog/Digital On Rails is optimization-centric but also has a calculator. 

Analog On Rails Demo

Here is a short Demo of Analog On Rails and Digital On Rails

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