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Enabling 5G Data Communication

Western Semiconductor’s SerDes IP is an NRZ embedded clock system tested from 65nm to 12nm with speeds ranging from 10.313 to 100Gbps. All of our SerDes cores are based on trusted ring PLLs to match a vast range of industry needs, while our library of 130+ standard cells allows us to rapidly customize special-purpose SerDes technology for high-performance applications.

Further Information

Western Semiconductor provides an extensive list of trusted IP. Please contact us for a detailed report on our SerDes technology.

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ASIC 3
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  • • NRZ system with embedded clock architecture
  • • Programmable 8bit and 16bit Serialization
  • • Deserialization available in 12nm to 65nm
  • • PCI Express and FIFO protocols available
  • • Analog 8bit CDR with LVDS
  • • CML input and output drivers
  • • PISO, PIPO, SIPO, and SISO components tested down to 12nm
  • • Guaranteed signal integrity with extremely low jitter of < 0.3 UI
  • • Consistent jitter tolerance in harsh mixed-signal environments
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