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Complete OA-based EDA suite. Industry compatible.
Semi-automatic migrations between 180-90-45-22-12nm
Schematic <=> layout synchronized at all times
Simulations synchronized. ElectroMigration made easy.
Simulate with parasitics at all times.
DRC and LVS correct by construction.
High quality automatic routing.
Easy UVM, synthesis, place, route, timing cockpit
Senior engineer is a one-stop-shop. No layout designer.
More what-if analysis. Less last minute scrambling
ANALOG/DIGITAL RAILS
ANALOG RAILS BASIC: SYNCHRONIZED, CORRECT BY CONSTRUCTION™
ANALOG / DIGITAL RAILS PREMIUM: REDUCE DESIGN TIME BY 10x WITH AUTOMATION
ANALOG RAILS BASIC: SYNCHRONIZED, CORRECT BY CONSTRUCTION™
Built on OA from scratch without legacy code. Analog Rails Basic uses the same database as Virtuoso. Never have a DRC or LVS violation. Cross probing and backannotation always. Infinite supply of multithreaded co-simulation licenses.
- OA native database. Plays with Virtuoso
- Built-in abutable backannotating PCells
- Graphical PCell generator
- Built-in stdcells with behavioral views
- Over 100 behavioral symbols
- Infinite AMS and HB simulator licenses
- Multithreaded transistor simulator
- Co-simulates with digital behavior
- Synchronized schematic, layout, wave
- DRC/LVS Correct By Construction™
- Cross probes always
- Highly accurate parasitic extraction
- Built-in analog and RF measurements
- Backannotate waveform's transient point
- Corners built in
DIGITAL RAILS: INCLUDES HUGE BUILT-IN LOGIC LIBRARY
ANALOG / DIGITAL RAILS PREMIUM: REDUCE DESIGN TIME BY 10x WITH AUTOMATION
ANALOG RAILS BASIC: SYNCHRONIZED, CORRECT BY CONSTRUCTION™
Includes synthesis with static timing optimization, automatic cell characterization, and fully integrated into the Analog Rails platform, all with cross probing, capacitance backannotation, 3D views, etc. Automatic feedback loops. No manual intervention is needed.
- Pushbutton RTL to Gate level synthesis
- Creates schematic with backannotation
- Place and route over 1M cells
- Automatic feedback loops. Let it bake
- Built-in logic cells synthesizable
- Automatic timing characterization
- Static Timing Optimization built-in
- Digital behavioral views of all cells
- Analog behavioral views of all cells
- Infinite System Verilog licenses
- Built-in power mesh and clock trees
- Auto pin based on parent's flight lines
- Co-simulates with Analog
- Integrated into analog system
Includes all functionality of Basic Rails
ANALOG / DIGITAL RAILS PREMIUM: REDUCE DESIGN TIME BY 10x WITH AUTOMATION
ANALOG / DIGITAL RAILS PREMIUM: REDUCE DESIGN TIME BY 10x WITH AUTOMATION
ANALOG / DIGITAL RAILS PREMIUM: REDUCE DESIGN TIME BY 10x WITH AUTOMATION
Reduce the former “full custom” IC design cycle from months down to hours. The Analog Rails mixed-signal platform is built around the automation tools. With the ability to go bottom to top to bottom to top quickly, do not fear last-minute changes... embrace them.
- Automatic migration tool
- Optimizer runs DC, AC, tran over corners
- Automatic differential structures
- Automatic electrically aware router
- Differential route with shields
- Differential aware density filler
- Automatic power supply mesh
- Automatic compactor
- Delete autoroutes, update, re-autoroute
- EM diagnostics. See EM% on the layout
- Click on 2 points. Get IR drop
- Cx and RCx wiring extraction
- Includes Basic and Digital Rails
- Sensitivity pinpoints measurement's culprit
- Monte Carlo runs on infinite licenses
Co-simulation along with an infinite number of Xyce/Spice licenses
Co-simulation along with an infinite number of Xyce/Spice licenses
Co-simulation along with an infinite number of Xyce/Spice licenses
Also included is Harmonic Balance and built-in RF measurements, such as transient noise. Users can also optionally simulate with 3rd party Hspice compatible simulators
Synthesis with a press of a button
Co-simulation along with an infinite number of Xyce/Spice licenses
Co-simulation along with an infinite number of Xyce/Spice licenses
Users can automatically generate the gate-level netlist and schematic based on their RTL code with a simple graphical interface in the same design environment as Analog Rails. It's so easy, an analog circuit designer can do it.
Optimization made easy
Co-simulation along with an infinite number of Xyce/Spice licenses
Measurements and analysis components in the schematic
Place your measurements and analysis components in our OA-based schematic, choose properties (including transistor operating regions) to optimize, and go to lunch. Return to see the final circuit sized according to spec over all corners. Runs AC, DC, and transients at the same time on multiple machines.
Measurements and analysis components in the schematic
Measurements and analysis components in the schematic
Measurements and analysis components in the schematic
Place settling time, overshoot, bandwidth, phase margin, risetime, and etc. components into the schematic, along with multiple analysis components (AC, DC, tran, pss, etc). Corner setups are included in the analysis components.
Digital Place and Route
Measurements and analysis components in the schematic
Automatic Analog Routing
Digital Rails makes digital place and route trivial due to built-in logic cells, synthesis, timing characterization, RCx, static timing tools, clock trees, and automatic flight line-based pin generators. The Digital Rails place and route tool automatically runs timing feedback loops and adjusts the layout, allowing users to click onto the PNR button and not require any manual intervention in order to come up with the fastest clock frequencies possible for the given RTL code being processed. The parasitics will always be backannotated into the schematic. The resulting block will instantiate perfectly onto the analog grid system for use at the higher level of the design.
Automatic Analog Routing
Measurements and analysis components in the schematic
Automatic Analog Routing
Our best feature. Low capacitive routes. Our multi-block and Transistor-level router also handles differential signals, with wire extensions and shields. We route 100% of the signals and ensure they are DRC correct. Routes are EM-friendly. Also includes a power supply mesh. Well taps are automatically generated. Preroutes optional.
Sensitivity Analysis
Automatic analog placement and differential structures
Huge built-in logic library
All measurements receive the variation and the largest culprits, both the devices and their parameters, causing the variation.
Huge built-in logic library
Automatic analog placement and differential structures
Huge built-in logic library
A vast set of process-independent parameterized (w_pmos, w_nmos, L) digital library topologies ships with Analog Rails. Standard cell layouts will be automatically generated. We don't need your digital layouts. Works in both the analog editor and digital P&R. The substrate (sub) terminal is isolated from the vssd terminal, where the users can optionally tie the substrate to the digital ground or isolate the supply from touching the main substrate. All logic cells contain behavioral views. Rise/fall times based on Cload, W, L, Cx.
Automatic analog placement and differential structures
Automatic analog placement and differential structures
Automatic analog placement and differential structures
Set auto-match on, press the "P" button, and enjoy the show. We know analog, and you can expect to see common centroid structures with guard rings, multiple dummies, and extended wells to reduce the STI stress and well proximity effects. Don't trust our layouts? Our product begins with "analog".
Manual DRC/LVS Correct By Construction™ layout
Manual DRC/LVS Correct By Construction™ layout
Automatic analog placement and differential structures
Much more powerful than DRC and LVS, the users cannot make a DRC or LVS violation. Primitives (fets, caps, resistors, bipolars, and differential structures) are generated automatically based on the technology file. No CAD scripts are required. Structures snap/repel/permute based on schematic connectivity. Collision avoidance on wiring. Once again, it is impossible for users to make violations.
Automatic Cell Characterization
Manual DRC/LVS Correct By Construction™ layout
Automatic Cell Characterization
Characterization is automatically done in Digital Rails. Upon PDK creation, merely define the corners, the slope steps, and the capacitor loads. The liberty formats will be automatically generated and will be used by our built-in static timing tool.
Advanced Layout Diagnostics
Manual DRC/LVS Correct By Construction™ layout
Automatic Cell Characterization
Cx backannotated into the schematic, RCx, selected net RCx, EM, IR drop, resistance between 2 points in the layout... we do it all!
DRC - Design Rule Check
DRC, LVS Correct By Construction™ ensures you can't make a mistake.