1) 10x labor efficiency. A $200K engineer will be worth $2M
2) Quicker time to market (tell your marketing group)
3) Expand portfolio (tell your marketing group)
4) More time to do trade-offs
5) More time to verify. Save mask sets, test/troubleshooting time
6) Circuit designers in control of their own layouts, which will improve the quality.
7) Ability to design bottom=>top=>bottom=>top. Why limit yourself?
8) Protect IP. No need to outsource.
9) Quickly create designs across multiple foundries
Watch how simple it is to automate Analog IC Layout Design
In this video, we demonstrate our three dimensional, interactive layout view.
Our SerDes technology includes an NRZ embedded-clock system running at 10Gbps with programmable 8bit and 16bit Serialization, with De-serialization available in 180nm - 12nm.
Our PLL cores include a General Purpose PLL, Fractional-N PLL, Multi-Phase PLL, and LC-PLL for low jitter, all of which have analog and digital versions for higher accuracy and faster locking speed.
We have various ADCs, DACs, filters, RISC-V cores, Compute-in-Memory tiles, ESD, and I/O available for our ASIC customers. We specialize in FINFET and FDSOI technologies.